1. Field of the Invention
The present invention generally relates to a method for fabricating semiconductor devices, and more specifically, to a method for fabricating a semiconductor device wherein precursor and deposition conditions of a bit line hard mask nitride film and a spacer nitride film are varied so that the nitride films are formed to have different etching ratios.
2. Description of the Related Art
FIG. 1 is a cross-sectional view illustrating a conventional method for fabricating a semiconductor device.
Referring to FIG. 1, a predetermined lower structure (not shown) is formed on a semiconductor substrate 10. Thereafter, a planarized interlayer insulating film (not shown) is formed on an entire surface of the resulting structure. A conductive layer (not shown) for a bit line is then formed on the semiconductor substrate 10. Next, a hard mask nitride film (not shown) is formed on the conductive layer. Thereafter, the hard mask nitride film and the conductive layer are patterned to form a stacked structure including a bit line 20 and a hard mask pattern 30. A spacer nitride film is then formed on the entire surface of the semiconductor substrate 10. Thereafter, the spacer nitride film is etched using a fluorine base gas to form a nitride spacer 50 on a sidewall of the stacked structure.
Next, an interlayer insulating film is formed on the entire surface of the semiconductor substrate 10 including the bit line 20. A storage node contact plug (not shown) for connecting a capacitor is then formed. In this case, an undesirable contact between the bit line 20 and the storage node contact plug may occur. In order to solve such a problem, an SAC (Self Align Contact) process having a high selectivity over the nitride film is performed while the bit line 20 is capped using the hard mask pattern 20 on the bit line nitride spacer 50 and the bit line 20, thereby forming the storage node contact plug. However, the hard mask pattern 30 and the nitride spacer 50 are over-etched to expose the bit line 20. As a result, an SAC process margin for forming the storage node contact plug is decreased and a possibility of the SAC process failure is increased.